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5 or greater, round up occurs in the destination. The unrounded quotient is stored in the most significant word of the math register. The remainder is placed in the least significant word of the math register. N7:23 0< N7:24 0< N7:25 0< Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • Updates to Arithmetic Status Bits Output Instruction The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated: Publication 1747-RM001C-EN-P - September 2001 4-10 Math Instructions With this Bit: The Processor: S:0/0 Carry (C) always resets.
S:0/1 Overflow (V) sets if division by zero or overflow is detected; otherwise resets. On overflow, the minor error flag is also set. The value 32,767 is placed in the destination. Exception: If you are using an SLC1 5/02 or higher processor and have S:2/14 (math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination. For floating point destinations, the overflow result remains in the destination. S:0/2 Zero (Z) sets if result is zero; otherwise resets; undefined if overflow is set.
S:0/3 Sign (S) sets if result is negative; otherwise resets. Output Instruction Subtract (SUB) Use the SUB instruction to subtract one value (source B) from another (source A) and place the result in the destination. Updates to Arithmetic Status Bits SUB Subtract Source A Source B Dest N7:17 0< N7:18 0< N7:19 0< The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated: Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • With this Bit: The Processor: S:0/0 Carry (C) sets if borrow is generated; otherwise resets (integer).